Solid-state memory capable of nonvolatile storage of charge, particularly in the form of EEPROM and flash EEPROM packaged as a small form factor card, has recently become the storage of choice in a variety of mobile and handheld devices, notably information appliances and consumer electronics products. Unlike RAM (random access memory) that is also solid-state memory, flash memory is non-volatile and retains its stored data even after power is turned off. In spite of the higher cost, flash memory is increasingly being used in mass storage applications. Conventional mass storage, based on rotating magnetic medium such as hard drives and floppy disks, is unsuitable for the mobile and handheld environment. This is because disk drives tend to be bulky, are prone to mechanical failure and have high latency and high power requirements. These undesirable attributes make disk-based storage impractical in most mobile and portable applications. On the other hand, flash memory, both embedded and in the form of a removable card is ideally suited in the mobile and handheld environment because of its small size, low power consumption, high speed and high reliability features.
EEPROM and electrically programmable read-only memory (EPROM) are non-volatile memory that can be erased and have new data written or “programmed” into their memory cells. Both utilize a floating (unconnected) conductive gate, in a field effect transistor structure, positioned over a channel region in a semiconductor substrate, between source and drain regions. A control gate is then provided over the floating gate. The threshold voltage characteristic of the transistor is controlled by the amount of charge that is retained on the floating gate. That is, for a given level of charge on the floating gate, there is a corresponding voltage (threshold) that must be applied to the control gate before the transistor is turned “on” to permit conduction between its source and drain regions.
The floating gate can hold a range of charges and therefore can be programmed to any threshold voltage level within a threshold voltage window. The size of the threshold voltage window is delimited by the minimum and maximum threshold levels of the device, which in turn correspond to the range of the charges that can be programmed onto the floating gate. The threshold window generally depends on the memory device's characteristics, operating conditions and history. Each distinct, resolvable threshold voltage level range within the window may, in principle, be used to designate a definite memory state of the cell.
In the usual two-state EEPROM cell, at least one current breakpoint level is established so as to partition the conduction window into two regions. When a cell is read by applying predetermined, fixed voltages, its source/drain current is resolved into a memory state by comparing with the breakpoint level (or reference current IREF). If the current read is higher than that of the breakpoint level, the cell is determined to be in one logical state (e.g., a “zero” state). On the other hand, if the current is less than that of the breakpoint level, the cell is determined to be in the other logical state (e.g., a “one” state). Thus, such a two-state cell stores one bit of digital information. A reference current source, which may be externally programmable, is often provided as part of a memory system to generate the breakpoint level current.
In order to increase memory capacity, flash EEPROM devices are being fabricated with higher and higher density as the state of the semiconductor technology advances. Another method for increasing storage capacity is to have each memory cell store more than two states.
For a multi-state or multi-level EEPROM memory cell, the conduction window is partitioned into more than two regions by more than one breakpoint such that each cell is capable of storing more than one bit of data. The information that a given EEPROM array can store is thus increased with the number of states that each cell can store. EEPROM or flash EEPROM with multi-state or multi-level memory cells have been described in U.S. Pat. No. 5,172,338.
The transistor serving as a memory cell is typically programmed to a “programmed” state by one of two mechanisms. In “hot electron injection,” a high voltage applied to the drain accelerates electrons across the substrate channel region. At the same time a high voltage applied to the control gate pulls the hot electrons through a thin gate dielectric onto the floating gate. In “tunneling injection,” a high voltage is applied to the control gate relative to the substrate. In this way, electrons are pulled from the substrate to the intervening floating gate.
The memory device may be erased by a number of mechanisms. For EPROM, the memory is bulk erasable by removing the charge from the floating gate by ultraviolet radiation. For EEPROM, a memory cell is electrically erasable, by applying a high voltage to the substrate relative to the control gate so as to induce electrons in the floating gate to tunnel through a thin oxide to the substrate channel region (i.e., Fowler-Nordheim tunneling.) Typically, the EEPROM is erasable byte by byte. For flash EEPROM, the memory is electrically erasable either all at once or one or more blocks at a time, where a block may consist of 512 bytes or more of memory.
The memory devices typically comprise one or more memory chips that may be mounted on a card. Each memory chip comprises an array of memory cells supported by peripheral circuits such as decoders and erase, write and read circuits. The more sophisticated memory devices operate with an external memory controller that performs intelligent and higher level memory operations and interfacing.
When a cell is programmed to a given state, it is subject to successive programming voltage pulses, each time adding incremental charge to the floating gate. In between pulses, the cell is read back or verified to determine its source-drain current relative to the breakpoint level. Programming stops when the current state has been verified to reach the desired state. The programming pulse train used may have increasing period or amplitude in order to counteract the accumulating electrons programmed into the charge storage unit of the memory cell. Programming circuits generally apply a series of programming pulses to a selected word line. In this way, a page of memory cells whose control gates are connected to the word line can be programmed together.
To achieve good programming performance, the initial programming voltage VPGM0 and the step size must be optimally chosen. If the initial programming voltage VPGM0 is chosen too low, it may require an excessive number of programming pulses to reach the target state. On the other hand if VPGM0 is chosen too high, especially in a multi-state memory, the programming may overshoot the target state in the first pulse. An optimum initial programming voltage VPGM0 would reach the target state in a few steps. The optimum VPGM0 is fairly sensitive to manufacturing variations and is traditionally determined by testing at the factory. This is a process known as VPGM0 trimming.
Conventionally, before shipping from the factory, a dedicated memory tester is setup to test a number of memory chips in parallel. One of the tests is to determine optimum initial programming voltages (VPGM0 trimmings.) Conventional VPGM0 trimmings are therefore performed by memory testers that are expensive dedicated machines. Moreover, they tend to test each word line in a piece-meal manner, moving to the next word line after the testing on the current one has been completed. In this manner, a page of memory cells on a word line is programmed in a program loop to test if it is programmable to a target pattern (e.g., “0000 . . . 0” where “0” denote a given programmed state). The program loop typically uses a series of programming voltage pulses from a first starting programming voltage. The page is then read back in a verify operation to determine if it has been properly programmed to a target pattern. If not program-verified, the page/word line of cells is erased and reprogrammed again in the next program loop with an incremented starting programming voltage. This process is repeated until the page is program-verified. In this way, the determination can be made of the value of the starting programming voltage that enables the page to be program-verified.
A number of trials in terms of program loops with increasing initial programming voltages may be needed to obtain the one that enables the page to be programmed properly. It can be seen that in conventional VPGM0 trimmings, the page must be erased before the next program loop is performed using an incremented starting voltage. Thus, the word line of memory cells carrying the page could be erased multiple times during these trials. Furthermore, all other word lines in the same erase block are also erase-cycled.
Non-volatile memory device has a limited life usage due to the endurance-related stress suffered each time the device goes through an erase/program cycle. For example, the endurance of a Flash EEPROM device is its ability to withstand a given number of program/erase cycles. The physical phenomenon limiting the endurance of non-volatile memory devices is the trapping of electrons in the active dielectric films of the device. Referring to FIG. 2, during programming, electrons are injected from the substrate to the charge storage unit through a dielectric interface. Similarly, during erasing, electrons are extracted from the charge storage unit through a dielectric interface. In both cases, some of the electrons are trapped by the dielectric interface. The trapped electrons oppose the applied electric field in subsequent program/erase cycles thereby causing the programmed threshold voltage to shift to a lower value and the erased threshold voltage to shift to a higher value. This can be seen in a gradual closure in the threshold window. The threshold window closure is what limits the practical endurance to approximately 104 program/erase cycles.
In a memory architecture where there are many word lines in each block, erasing a word line of cells multiple times would entail erasing the rest of the word lines in the same block the same number of times. If these other word lines in the block are also being tested, the number of times the block is erased would go up geometrically. For example, if it takes roughly 10 trials for each word line, and there are 64 word lines in each block, it will mean the block will suffer erase cycling of a total of 640 times. Furthermore, VPGM0 trimming is also performed to cover a number of other variables. For example, the word line may carry multiple physical pages as well as multiple logical pages. The word lines near the block boundary may have slightly different programming characteristics compared to the ones in the core region. These variations could contribute another factor of 10 to the number of trimmings needed. Thus, conventional VPGM trimmings at the factory could consume as much as several thousand endurance cycles of a memory device. As much as half of a memory device's life usage could be used up before it gets to a customer.
Therefore there is a general need for high performance and high capacity non-volatile memory. In particular, there is a need for a non-volatile memory with optimally set starting programming voltages, yet without the expense of excessively endurance cycling the memory to determine them.